1. Field of the Invention
The present invention generally relates to a method for manufacturing a chip-size package (CSP), and the chip-size package produced by the method, and more particularly to a method for manufacturing a chip-size package using a multi-layer laminated lead frame.
2. Background of the Related Art
The miniaturization and multi-funtionalization of electronic equipment has resulted in the advancement of manufacturing technologies for semiconductor devices. This advancement includes progress in packaging technology toward high mounting density, high processing speed and miniaturization.
The mounting density of the chip package on a substrate has gradually increased, as the structure of the package has changed from the insert mounting type to the surface mounting type (SMT).
Due to this recent trend toward high mounting density of the package on a substrate, the kind of package has been changed from dual inline package (DIP) to small outline package (SOP), and then to thin small outline package (TSOP) whose thickness is as small as one-half that of a conventional SOP.
Particularly, in the case of the memory semiconductor chip, the size of the semiconductor chip increases as the capacity increases. If the size of the semiconductor chip increases, it is difficult to meet the reliability requirement of the package with the conventional plastic package technology.
Accordingly, a so-called chip-size package which has the same size or is slightly larger than the chip itself has been developed to satisfy this need.
The chip-size package has some advantages in that it is smaller and thinner than any other package type, it provides better electrical performance than most SMT packages due to shorter leads and lower lead inductance, and that it is easier to handle than a bare chip.
Many semiconductor manufacturers are developing various types of chip-size packages. The chip-size packages are classified into flexible circuit interposer type, rigid substrate interposer type, transfer molded, type, custom lead frame type, and TCP (Tape Carrier Package) type. Among these chip-size packages, the chip-size package employing LOC (Lead On Chip) technology can meet the demand for high density of the package.
An example of the chip-size package employing LOC technology is as follows. FIG. 1 is a cross-sectional view showing an example of the chip-size package employing the LOC technology, and FIG. 2 is an enlarged view of the lead portions of the chip-size package in FIG. 1.
Referring to FIG. 1 and FIG. 2, an active surface of the semiconductor chip 72 is attached to the lower surface of the leads 76 by using a double-sided adhesive tape 78 in the chip-size package 70. Because the upper surfaces of the leads 76 were partially etched by the half-etching method in the manufacturing process of the lead frame, the inner portions of the leads 76 are thin and the outer portions of the leads 76 are thick. Accordingly, the leads 76 are L-shaped.
The upper surfaces of the thin portions of the leads 76 and the bonding pads 74 of the semiconductor chip 72 are electrically interconnected by gold (Au) wires 80. The semiconductor chip 72 and the leads 76 including the bonding pads 74 and the gold wires 80 are encapsulated with an epoxy molding compound 82 so that the semiconductor chip 72 and the gold wires 80 are protected from the external environment, and the upper surfaces of the thick portions of the leads 76 are exposed to the outside for the next level electrical connection such as mounting to a substrate.
The conventional chip-size package using the lead frame which is manufactured by using the half-etching method as shown above has at least one drawback, in that the manufacturing process of the lead frame is complicated and expensive, compared to a lead frame which is manufactured by using a stamping method.